`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/01/02 15:43:26
// Design Name: 
// Module Name: shift
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module shift(
    input wire [31:0] a,
    input wire signed[31:0] b,
    input wire [4:0] c,
    input wire star,
    input wire [3:0] op,
    output wire [31:0] shift_out
    );
    
    reg[31:0] shift_ans;
    
    always @(*)begin
        case(c)
            4'b0001: shift_ans <= b<<c;//sll
            4'b0010: shift_ans <= b>>c;//srl
            4'b0011: shift_ans <= b>>>c;//sra
            4'b0100: shift_ans <= b<<a; //sllv 
            4'b0110: shift_ans <= b>>a;//srlv 
            4'b0111: shift_ans <= b>>>c;//srav
            default: shift_ans <= 32'b0;
        endcase
    end
    
    assign shift_out = star? shift_ans:32'b0;
endmodule
